The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a capacitor.
With an increase in integration density of a DRAM in which one memory cell is constituted by one transistor and one capacitor, in order to obtain a required storage charge capacitance within a limited occupied area, a method of making the surface of an electrode uneven to increase the effective surface area of the electrode is proposed. As a prior art for making the electrode surface of a capacitor uneven, a method of manufacturing a DRAM memory cell having a stacked capacitor described in Japanese Patent Laid-Open No. 3-139882 will be described below with reference to FIG. 10. Note that FIG. 10 shows the memory cell.
A field oxide film 2 for performing element isolation by a LOCOS method is formed on a p-type semiconductor substrate 1. Thereafter, the resultant structure is dried or oxidized with steam to form a gate oxide film 3 having a thickness of about 10 to 30 nm on the active region of the substrate 1. The first polysilicon film 4 having a thickness of about 100 to 300 nm is deposited on a region in which a memory cell is to be formed by an LPCVD method or the like, and phosphorus (P) is doped in the first polysilicon film 4 at a concentration of about 10.sup.20 cm.sup.-3 by thermal diffusion using POCl.sub.3 as a source. Thereafter, a resist is patterned using a normal photolithographic technique, and the polysilicon film 4 is etched using the patterned resist as a mask to form word lines 4, including gate electrodes on the gate oxide films 3, of memory cells respectively located on the field oxide film 2 and the gate oxide films 3.
Arsenic (As) is ion-implanted in the resultant structure using the word lines 4 and the field oxide film 2 as masks, and the resultant structure is annealed to form n.sup.+ -type diffusion layers 5a and 5b each having an arsenic concentration of about 10.sup.20 cm.sup.-3 in the surface portion of the substrate 1. Thereafter, a silicon oxide film 6 serving as a first insulating interlayer 6 having a thickness of 100 to 300 nm is deposited on the entire surface of the resultant structure by an atmospheric-pressure CVD method or the like, and an opening is formed in the silicon oxide film 6 on a predetermined portion of the n.sup.+ -type diffusion layer 5a by a dry etching technique using, as a mask, a resist patterned by a normal photolithographic technique, thereby forming a contact hole 7.
Subsequently, a refractory metal silicide film, e.g., a WSi.sub.x (x=2.0 to 3.0) film 8, prospectively serving as a storage node of a memory cell is formed on the entire surface of the resultant structure by a sputtering method or the LPCVD method to have a thickness of about 100 to 200 nm. Thereafter, a second polysilicon film 9 having a thickness of 50 to 150 nm is formed on the WSi.sub.x film 8 by the LPCVD method, and phosphorus is doped in the second polysilicon film 9 at a concentration of about 10.sup.20 cm.sup.-3 by thermal diffusion using POCl.sub.3 as a source. When an impurity is doped in a polysilicon film, the impurity is segregated at grain boundaries or crystal defects such as twins in crystal grains, and portions each having a high impurity concentration are formed in the polysilicon film.
The second polysilicon film 9 is dipped in a solution of phosphoric acid heated to about 170.degree. C. for 10 to 20 minutes. An etching process using the heated solution of phosphoric acid has an etch rate whose impurity concentration dependency is large. For this reason, in this etching process, portions each having a high impurity concentration are selectively etched. In this manner, the grain boundary of the second polysilicon film 9, i.e., polysilicon at crystal grain boundary is particularly etched, and an uneven portion is formed in the surface of the second polysilicon film 9. At this time, in order to form satisfactory an uneven portion, the phosphorus concentration of the second polysilicon film 9 must be set to be 6.times.10.sup.20 cm.sup.-3 or more. In addition, when a time taken for dipping the second polysilicon film 9 in the solution of phosphoric acid is prolonged, the peak-to-peak difference of the uneven portion increases. In this case, for example, even when polysilicon in each recessed portion is entirely etched, the underlying WSi.sub.x film 8 functions as an etching stopper. In addition, the second polysilicon film 9 is connected by the WSi.sub.x film 8, and disconnection caused by the uneven portion does not occur in the second polysilicon film 9. Subsequently, the second polysilicon film 9 and the WSi.sub.x film 8 are patterned using a dry etching technique using, as mask, a resist patterned by a normal photolithographic technique, and a lower electrode 9 for a memory cell located between the word lines 4 and between the word lines 4 is formed. Thereafter, an Si.sub.3 N.sub.4 film 10 prospectively serving as a capacitor insulating film is oxidized on the entire surface of the resultant structure by the LPCVD method or the like to have a thickness of about 5 to 10 nm, and the Si.sub.3 N.sub.4 film 10 is oxidized at 800.degree. to 900.degree. C. in a steam atmosphere for 30 to 60 minutes to form an oxide film 11, having a thickness of 1 to 2 nm, for increasing the breakdown voltage of the Si.sub.3 N.sub.4 film 10. Thereafter, a third polysilicon film 12 having a thickness of 200 to 300 nm is formed on the oxide film 11 by the LPCVD method, and phosphorus is doped in the third polysilicon film 12 at a concentration of 4.times.10.sup.20 to 6.times.10.sup.20 cm.sup.-3 by thermal diffusion using POCl.sub.3 as a source.
Thereafter, the third polysilicon film 12 is patterned by a photolithographic technique and a dry etching technique to form an upper electrode 12 covering the lower electrode 9, thereby forming the capacitor of the DRAM memory cell. The capacitor formed as described above exhibits a storage charge capacitance about 1.2 to 1.4 times that of a capacitor on which an uneven portion is not formed.
Thereafter, a second, insulating interlayer 13 consisting of BPSG or the like is deposited on the entire surface of the resultant structure by the atmospheric-pressure CVD method to have a thickness of about 600 to 800 nm, and then is annealed at about 900.degree. C. to smooth the second insulating interlayer 13. The second insulating interlayer 13 on a portion of the n.sup.+ -type diffusion layer 5b is selectively removed by etching to form a contact hole 14. Thereafter, an Al film 15 is deposited on the entire surface of the resultant structure by a sputtering method to have a thickness of about 1,000 nm, and the Al film 15 is patterned to form a bit line. In addition, a protective film is coated on the surface of the bit line, thereby completing a DRAM memory cell.
Problems to be solved by the present invention will be described below with reference to FIG. 9.
As has been described above, when an impurity is doped in a polysilicon film, the impurity is segregated at crystal grain boundaries or crystal defects such as twins in crystal grains, and portions each having a high impurity concentration are formed in the polysilicon film. In the prior art, using that portions each having a high impurity concentration is selectively etched by a heated solution of phosphoric acid, i.e., that each of the portions has an etch rate whose impurity concentration dependency is large, an uneven portion is formed on the polysilicon film surface by a single etching process.
In the prier art, a problem posed in a case wherein a ratio (selectivity ratio) of the etch rate of a portion having a high phosphorus concentration to the etch rate of a portion having a low phosphorus concentration is high, i.e., 10 or more, a problem posed in a case wherein the ratio is intermediate, i.e., 2 to 10, and a problem posed in a case wherein the ratio is low, i.e., 1 to 2 will be described below.
When the etching selectivity ratio is high (the impurity concentration dependency of an etch rate is large) is high, for example, assuming that the polysilicon film before an etching process is set as shown in FIG. 9A, the etching process forms groove-like (slit-like) recessed portions each having a width of about 10 nm at grain boundaries as shown in FIG. 9B.
Since the minimum thickness of a capacitor insulating film is about 5 nm, when the width of each of recessed portions to be formed is very small, the recessed portions are buried with the capacitor insulating film. For this reason, the surface area of a counterelectrode (upper electrode) does not easily increase. When portions each having a high impurity concentration are segregated at defects in crystal grains, a porous silicon layer 16 having a several-nm-level structure is formed on the surfaces of the crystal grains. The porous silicon layer 16 is easily depleted because the porous silicon layer 16 has a very fine structure, thereby causing a decrease in storage charge capacitance. In addition, since needle-like projecting portions are present on the surface of the porous silicon layer 16, electric field concentration locally occurs in a capacitor insulating film, thereby causing an increase in leakage current or degradation of reliability. Moreover, the projecting portions form pinholes, thereby decreasing a yield.
A case wherein an etching selectivity ratio is 2 to 10 is shown in FIG. 9C. In this manner, when the selectivity ratio is set to be an intermediate value, the width of each recessed portion increases, but the depth of each recessed portion decreases. In addition, although the thickness of the porous silicon layer 16 decreases, the porous silicon layer 16 cannot be easily prevented from being formed as long as selective etching is performed. Therefore, the above problem is left unsolved.
When an etching process having a selectivity ratio of about 1 to 2 is performed, as shown in FIG. 9D, a surface on which a porous silicon layer is rarely present can be obtained. However, the uneven portion is also moderated, and, therefore, an electrode surface area rarely increases.
As described above, in the prior art in which the uneven portion is formed on the lower electrode 9 by a single etching process, the depth and width of each recessed portion cannot be independently controlled, and a capacitor which has a sufficiently controlled surface shape and satisfies conditions such as a high storage charge capacitance, a high yield, a low leakage current, and high reliability cannot be easily realized.